Conventional flash memory cells store a charge on a floating gate that may, for example, be doped polysilicon. The stored charge changes a threshold voltage (Vt) of the memory cell. In a “read” operation, a read voltage is applied to the gate of the memory cell, and the corresponding indication of whether the memory cell turns on (e.g., conducts current) indicates the programming state of the memory cell. For example, a memory cell that conducts current during the “read” operation may be assigned a digital value of “1,” and a memory cell that does not conduct current during the “read” operation may have a digital value of “0” assigned. Charge may be added to and removed from the floating gate to program and erase the memory cell (e.g., to change the memory cell value from “1” to “0”).
Another type of memory uses a charge-trapping structure rather than a conductive gate material used in floating gate devices. When a charge-trapping layer is programmed, the charge may be trapped so that it does not move through the non-conductive layer. The charge may therefore be retained by the charge-trapping layer until the memory cell is erased, thereby retaining the data state without requiring a continuous source of electrical power to be applied. These charge-trapping cells can be operated as two-sided cells. In other words, because the charge does not move through the non-conductive charge trapping layer, charge can be localized on different charge-trapping sites. Thus, a so called multi-bit cell (MBC) may be created, which can increase the amount of data that can be stored in a memory device without consuming more space.
FIG. 1 illustrates an example of a charge trapping memory cell 10. As shown in FIG. 1, the charge trapping memory cell 10 may include a gate 14 and symmetrical source/drain regions (e.g., S/D regions 16 and 18) that are in communication with a semiconductor channel 20. The semiconductor channel 20 and the gate 14 may be separated from a charge trapping layer 12 by insulation layers (e.g., oxide regions 13 and 15), respectively. In this example configuration, the left storage side 22 of the charge trapping layer 12 may be programmed to multi-level storage side and the right storage side 24 of the charge trapping layer 12 may be programmed to multi-level storage side.
The illustrated left storage side 22 and right storage side 24 may be programmed to four states (i.e., including states 00, 01, 10 and 11) and store two bits data. Since accumulation of charge is an important feature of multi-bit programming, with more precise charge placement in the charge trapping layer 12, higher numbers of bits and states may be accurately achieved. A particular bit can typically be programmed, for example, by applying a potential to the gate 14 with one of the S/D regions 16 and 18 (e.g., region 18) acting as a drain and the other of the S/D regions 16 and 18 (e.g., region 20) acting as the source. The accumulation of charge at the particular side alters the threshold voltage of the left storage side 22 or right storage side 24. For example, to read the value 01 (also referred to as Level 1 for purposes of illustration), a potential may be applied to the cell that is between the right-most point of the Level 1 distribution and the left-most point of the Level 2 distribution. The region or window of values that the potential may have to comply with these criteria is called a “read window.”
The threshold voltage of the left storage side may be increased when programming the right storage side. The increase in threshold voltage at the left storage side is shown by the dashed line in FIG. 2 and is indicative of a phenomenon known as “the second bit effect.” In order to accurately program multi-bit cells, incremental stepping of the drain line (bit line) voltage is often implemented (e.g., via application of uniform pulses to the bit line). In some cases, a program pulse is followed by a read operation in order to verify the level programmed into the cell. As the desired threshold voltage is approached, the voltage step of the pulse may be decreased. However, this may still result in relatively wide programming distributions. In general, a wider distribution correlates to a smaller read window. Furthermore, as discussed above, applying a potential to the cell typically affects both bits due to the second bit effect.
When an array of cells is arranged, the drain lines (bit lines) may be connected as well as the gate lines (word lines) and source lines. When one tries to program the entire array, program disturb may impact neighboring cells due to capacitive coupling between the cells that may change the charge levels stored in the respective bits. There are numerous mechanisms that have been developed in an effort to reduce the impact of the second bit effect and program disturb. Some of these mechanisms involve the application of different voltages to the source lines, bit lines or word lines. Thus, it may be desirable to provide an improved mechanism for programming a multi-level cell.